Design , Implementation and Analysis of Efficient FPGA based Physical Unclonable Functions

With the advent of Internet of Things (IoTs), secure communication between devices is a big challenge. Billions of new devices and sensors are going to be connected to the Internet. To ensure secure communication among these devices we need hardware primitives that are well suited to the requirements of IoTs. Recent research has led to an increased interest in security measures, especially in solutions that are physically unique and unclonable. Physical Unclonable Function (PUF) has been found to be a strong candidate for this purpose. Since PUF extracts the inherent manufacturing variations of a hardware chip, therefore it can be used as a fingerprint of an integrated circuit, such as Field Programmable Gate Array (FPGA). Eventually these fingerprints can be used to authenticate FPGA devices and also to generate secure keys for cryptographic functions. This thesis describes the development of efficient and reliable PUFs for FPGAs. Novel PUFs have been designed for this purpose. Furthermore, the dissertation covers the generation and analysis of PUF responses in a more coherent and systematic way than the state-of-the art methods reported in the literature to date. For the generation of PUF responses, different bit-generation schemes have been used and their performance metrics have been compared among each other. This novel study was performed to determine the best scheme among the most popular schemes reported by other researchers to date. Comprehensive software scripts have been developed for all investigated schemes. Similarly for the analysis, new metrics have been proposed for the evaluation of PUF responses. Additionally, comprehensive software scripts have been developed to analyze PUF responses. These open-source scripts can be applied to any type of PUF. Design, development, implementation and testing of two major types of PUF have been carried out. One of them is a memory based PUF: SR-Latch based design. The second is a delay based PUF: Ring oscillator based design. Both designs have been thoroughly tested on FPGA devices. Performance metrics of both designs have been presented and compared with the equivalent results for state of the art PUFs. Experiments were carried out using FPGA devices from two major vendors, Xilinx and Altera. This study was performed to investigate the applicability and portability of our designs. One of the major requirements of PUF intended for IoT applications is that the device area must be efficiently utilized. The current state of the art PUFs are expensive in terms of FPGA resource utilization. Therefore, in this work a highly efficient PUF has been developed and tested on FPGAs. Additionally this PUF has been shown to be very reliable for use at different environmental conditions. This feature makes it attractive for IoT applications because of the broad range of temperature and voltage variations these devices are exposed to. To regenerate the same PUF response under different conditions we used a fuzzy extractor based on the BCH error correction scheme. We also investigated other schemes and compared them from the reliability and resource utilization point of view. Lastly we presented a prototype of an efficient SR-Latch based PUF design, which demonstrates a factor of two improvement in area over the state of the art, thus making this PUF very attractive for IoT applications. This prototype is able to reliably and securely generate a unique and random 128-bit cryptographic key. A copy of this doctoral dissertation is on reserve at the Johnson Center Library